Test Pattern Generation Using LFSR with Reseeding Scheme for BIST Designs

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Provided by: International Association of Scientific Innovation and Research (IASIR)
Topic: Software
Format: PDF
In this paper, the authors present LFSR reseeding scheme for BIST. A time-to-market efficient algorithm is introduced for selecting reseeding points in the test sequence. This algorithm targets complete fault coverage and minimization of the test length. Functional broadside tests that avoid over testing by ensuring that a circuit traverses only reachable states during the functional clock cycles of a test. These consist of the input vectors and the corresponding responses. They check for proper operation of a verified design by testing the internal chip nodes.
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