Test Procedures for Synchronized Oscillators Network CMOS VLSI Chip

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Provided by: Creative Commons
Topic: Hardware
Format: PDF
In this paper, the authors present test procedures designed for Application-Specific Integrated Circuit (ASIC) CMOS VLSI chip prototype that implements a synchronized oscillator neural network with a matrix size of 32x32 for object detecting in binary images. Networks of synchronized oscillators are recently developed tool for image segmentation and analysis. This paper briefly introduces synchronized oscillators network. Basic chip analog building blocks with their test procedures and measurements results are presented. In order to do measurements, special basic building blocks test structures have been implemented in the chip.
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