Test Scheduling of Stacked 3D SoCs with Thermal Aware Considerations
Today's electronic designs have become prone to errors and defects due to the ever increasing complexity and compactions. This has resulted into imparting of much more importance to VLSI testing. Testing is mandatory and has to be performed on each manufactured product. Low cost and good defect coverage are the basic goals of testing, which are again determined by fault models, test volume and time. Time depends on how the tests are scheduled. Test scheduling has therefore become an important area of research. The work here is devoted to test scheduling of 3D SoCs taking into account the severe challenge it faces for its adoption i.e. the thermal management problem.