Testing of Embedded Processor in WSN Nodes

Provided by: International Journal of Emerging Technology and Advanced Engineering (IJETAE)
Topic: Mobility
Format: PDF
In Wireless Sensor Networks (WSN) possibility of intermittent faults, failure of nodes, Battery replacement-charging problem and energy optimization problem occur. The issues in the processor design are modeling, scheduling and testing, hardware constraints, power efficiency, power saving modes of operations and error control coding scheme. To handle this energy - power consumption, error control coding scheme in WSN Processor Design, a SBST Online testing of processors is used. SBST routines-low cost testing of processors which are downloading in to the WNS nodes and also to the Flash memory to test the processor. This increases the energy gain for offering clock gating and frequency scaling features. To optimize the energy of WSN Processor, the methodology used is Energy Aware Loop Synthesis, Loop Transformation, and Instruction Substitution.

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