Testing of N-Stage 1 Bit Per Stage Pipelined ADC Using Test Input Regeneration

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Provided by: WSEAS
Topic: Hardware
Format: PDF
Analog-to-Digital Converters (ADCs) became an integral part in most systems. The Pipelined ADC (PADC) is one of the preferred ADCs; it is perfect for applications requiring high speed and medium resolution. Hence, the test of ADCs in general as well as PADCs is not only interesting but mandatory; the need for a low cost and efficient test technique in order to test the PADC is increasing. This paper is on proposing a new efficient test technique fitting an n-stage PADC test.
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