Provided by: International Journal of Engineering, Science and Innovative Technology (IJESIT)
Date Added: Nov 2013
Current VLSI circuits, e.g., data path architectures or digital signal Processing chips frequently contain arithmetic modules such as accumulators, Arithmetic Logic Units (ALUs). The basic idea of ABIST is to utilize accumulators for built-in testing which is compression of the CUT responses or generation of test patterns and has been shown to result in low hardware overhead and low impact on the circuit speed. In this paper, an accumulator-based test pattern generation scheme that compares with the previously proposed schemes and it was proved that the test vectors generated by an accumulator whose inputs are driven by a constant pattern can have acceptable pseudorandom individuality, if the input pattern is appropriately selected.