The Design and Verification of the IEEE1394 Link Core Based on FPGA

Provided by: AICIT
Topic: Hardware
Format: PDF
The protocol architecture, working principle of link-layer and the composing and function of link core are described in detail. RTL (Register Transfer Level) design for IEEE 1394 link core based on Cyclone serial FPGA (Field Programmable Gate Array) of Altera is proposed. And logical design, functional simulation and timing verification mainly on the transfer of asynchronous data are emphatically studied. From the simulation waveform, it can be seen that the design coincides with the protocol's release and the operations for the transfer of all kinds of asynchronous packet is implemented correctly.

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