UNIVERSITY OF CARTAGENA
The network-on-chip concept is a direct result of the complexity of recent and future System-On-Chips (SoCs). In fact, multiplying the core's number of the same chip has conducted to internal signals communication problems. Conventional buses were not able to manage too many cores with too many signals. Moreover those signals could be heterogeneous in terms of functionality (control, data, and addresses), in terms of speed (different throughputs of internal cores) and the authors are talking here about multiple clock domains or the most important in terms of priority. Unfortunately, the classic bus architecture like multiple master multiple slave configuration were inefficient to face this multitude of complexity and heterogeneity of such systems.