University of Colorado
Data prefetching of regular access patterns is an effective mechanism to hide the memory latency for modern microprocessors. However, to be included in architecture design, prefetching systems must be cost-effective and have little impact to the microarchitecture. For example, while many proposed prefetching systems use the full Program Counter (PC) to help detect patterns with arbitrary strides; such systems are impractical and prohibitive. To overcome the issues related to using the entire PC for effective prefetching, this paper combines other instruction attributes with a small subset of the PC to help detect the regularity in program data accesses.