The Design of Serial ATA Bus Control Chip

In a PC system, external storage interface is still a bottleneck in spite of its continuous improving performance, in contrast to the fast development of CPU, memory and graphic chips. The transfer rate in ATA protocol has been improved drastically from the beginning 3.3MB/s to current 133MB/s, but the plate electrode of a parallel interface is inevitably puzzled by clock skew, which limit the increasing of frequency and transfer rate cannot be improved. Serial ATA protocol is compatible with parallel ATA protocol in software layer.

Provided by: Journal of Computers (JCP) Topic: Hardware Date Added: Apr 2010 Format: PDF

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