The DIMM Tree Architecture: A High Bandwidth and Scalable Memory System

The demand for capacity and off-chip bandwidth to DRAM will continue to grow as the authors integrate more cores onto a die. However, as the data rate of DRAM has increased, the number of DIMMs supported on a multi-drop bus has decreased. Therefore, traditional memory systems are not sufficient to meet both these demands. They propose the DIMM tree architecture for better scalability by connecting the DIMMs as a tree. The DIMM tree architecture is able to grow the number of DIMMs exponentially with each level of latency in the tree. They also propose application of Multiband Radio Frequency Interconnect (MRF-I) to the DIMM tree architecture for even greater scalability and higher throughput.

Provided by: Institute of Electrical & Electronic Engineers Topic: Storage Date Added: Nov 2011 Format: PDF

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