Provided by: Cornell University
Date Added: Mar 2012
One of the most demanding challenges for the designers of parallel computing architectures is to deliver an efficient network infrastructure providing low latency, high bandwidth communications while preserving scalability. Besides off-chip communications between processors, recent multi-tile (i.e. multi-core) architectures face the challenge for an efficient on-chip interconnection network between processor's tiles. In this paper, the authors present a configurable and scalable architecture, based on their Distributed Network Processor (DNP) IP Library, targeting systems ranging from single MPSoCs to massive HPC platforms.