The Effect of Interconnect Design on the Performance of Large L2 Caches

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Provided by: The University of Tulsa
Topic: Hardware
Format: PDF
The ever increasing sizes of on-chip caches and the growing domination of wire delay have changed the traditional design approach of the memory hierarchy. Many recent proposals advocate splitting the cache into a large number of banks and employ an on-chip network to allow fast access to nearby banks (referred to as Non-Uniform Cache Architectures (NUCA)). While these proposals focus on optimizing logical policies associated with a cache design, initial design choices do not include the complexity of the network.
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