Provided by: Association for Computing Machinery
Date Added: Sep 2012
Off-chip main memory has long been a bottleneck for system performance. With increasing memory pressure due to multiple on-chip cores, effective cache utilization is important. In a system with limited cache space, the authors would ideally like to prevent cache pollution, i.e., blocks with low reuse evicting blocks with high reuse from the cache, and cache thrashing, i.e., blocks with high reuse evicting each other from the cache. In this paper, they propose a new, simple mechanism to predict the reuse behavior of missed cache blocks in a manner that mitigates both pollution and thrashing.