The FAST Methodology for High-Speed SoC/Computer Simulation

Provided by: University of Texas at Arlington
Topic: Hardware
Format: PDF
In this paper, the authors describe the FAST methodology that enables a single FPGA to accelerate the performance of cycle-accurate computer system simulators modeling modern, realistic SoCs, embedded systems and standard desktop/laptop/server computer systems. The methodology partitions a simulator into a functional model that simulates the functionality of the computer system and a predictive model that predicts performance and other metrics. The partitioning is crafted to map most of the parallel work onto the hardware-based predictive model, eliminating much of the complexity and difficulty of simulating parallel constructs on a sequential platform.

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