The Implementation of a Pipelined Floating-Point Cordic Coprocessor on NIOS II Soft Processor

Provided by: Institute of Research and Journals (IRAJ)
Topic: Hardware
Format: PDF
In this paper, the authors discuss the implementation of a pipelined floating-point CO-ordinate Rotation Digital Computer (CORDIC) coprocessor using Field Programmable Gate Array (FPGA) to accelerate the computation speed in solving elementary functions on NIOS II soft processor. Examples of the elementary functions are trigonometry and hyperbolic functions, exponential, natural logarithm, square root as well as multiplication and division. In order to enhance its functionality, an argument reduction algorithm was introduced to expand the convergence limit for the inputs.

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