The Implementation of High-Speed Floating-Point DBF Based on FPGA

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Provided by: AICIT
Topic: Hardware
Format: PDF
In this paper, an implementation of high-speed floating-point digital beamformer on FPGA is proposed to implement 64 beams and 16 sensors of 50kHz linear array in multibeam echosounder. This implementation is based on single precision floating-point units for the accurate computation. Proposed pipelined architectures decrease the chip area requirements and cause to increase the throughput of the digital beamformer. Comparison of the proposed approach with another approach based on the Xilinx IP core generator modules shows that the former technique outperforms the latter in terms of latency and speed.
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