The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays

Provided by: University of Texas at Arlington
Topic: Hardware
Format: PDF
Improvements in microprocessor performance have been sustained by increases in both Instruction Per Cycle (IPC) and clock frequency. In recent years, increases in clock frequency have provided the bulk of the performance improvement. These increases have come from both technology scaling and deeper pipelining of designs. In this paper, the authors examine for how much further reducing the amount of logic per pipeline stage can improve performance. The results of this study have significant implications for performance scaling in the coming decade.

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