The Virtual Write Queue: Coordinating DRAM and Last-Level Cache Policies

Provided by: Association for Computing Machinery
Topic: Storage
Format: PDF
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU's data needs, and are mostly oblivious to the main memory. In this paper, the authors demonstrate that the era of many-core architectures has created new main memory bottlenecks, and mandates a new approach: coordination of cache policy with main memory characteristics. Using the cache for memory optimization purposes, they propose a virtual write queue which dramatically expands the memory controller's visibility of processor behavior, at low implementation overhead.

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