Thermal-Reliable 3D Clock-Tree Synthesis Considering Nonlinear Electrical-Thermal-Coupled TSV Model
3D physical design needs accurate device model of Through-Silicon-Vias (TSVs). In this paper, physics-based electrical-thermal model is introduced for both signal and dummy thermal TSVs with the consideration of nonlinear electrical-thermal dependence. Taking thermal-reliable 3D clock-tree synthesis as a case-study to verify the effectiveness of the proposed TSV model, one non-linear programming-based clock-skew reduction problem is formulated to allocate thermal TSVs for clock-skew reduction under non-uniform temperature distribution. With a number of 3D clock-tree benchmarks, experiments show that under the nonlinear electrical-thermal TSV model, insertion of thermal TSVs can effectively reduce temperature-gradient introduced clock-skew by 58.4% on average and has 11.6% higher clock-skew reduction than the result under linear electrical-thermal model.