Through-Silicon-Via-Induced Obstacle-Aware Clock Tree Synthesis for 3D ICs

In this paper, the authors present an obstacle-aware clock tree synthesis method for Through Silicon Via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that various types of TSVs become obstacles during 3D clock routing including signal, power/ground and clock TSVs. Some of these TSVs become placement obstacles, i.e., they interfere with clock buffers and clock TSVs; while other TSVs become routing obstacles, i.e., clock wires cannot route through them.

Provided by: Institute of Electrical and Electronics Engineers Topic: Hardware Date Added: Dec 2011 Format: PDF

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