Vienna University of Economics and Business
In this paper, the authors propose a first step towards a time predictable computer architecture for single Chip Multi-Processing (CMP). CMP is the actual trend in server and desktop systems. CMP is even considered for embedded real-time systems, where Worst-Case Execution Time (WCET) estimates are of primary importance. They attack the problem of WCET analysis for several processing units accessing a shared resource by support from the hardware. In this paper, they combine a time predictable java processor and a Direct Memory Access (DMA) unit with a regular access pattern.