Timing Analysis Techniques Review for Sub-30 nm Circuit Designs

Provided by: Journal of Semiconductor Technology and Science (JSTS)
Topic: Hardware
Format: PDF
With continuous CMOS technology scaling, the number of devices per unit area have increased dramatically. This increased degree of integration enables user to design more powerful electronic devices. However, circuit designs of less than 30nm causes many problems that now have significant impacts on circuit performance. One of these key design problems is process variation. Increasing fluctuations as a result of manufacturing processes have introduced unavoidable and significant uncertainty in circuit performance; hence, ensuring manufacturability has been identified as one of the top priorities of today's IC design process.

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