Provided by: Technical University of Lodz
Date Added: Oct 2013
A processor architecture is said to be timing anomalous when a locally favorable event (e.g. cache hit) could result in a globally unfavorable event (e.g. longer execution time) and vice versa. Timing anomalies in single-core processors have been theoretically explained and well understood phenomenon. This paper presents new timing anomalies which occur in multi-core architectures due to the interference on the shared resources. The authors derive formulation to capture these anomalies and provide practical evidences using real applications from the Malardalen WCET benchmark suit executing on NIOS II multi-core architecture on an Altera FPGA.