Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation

Provided by: AICIT
Topic: Hardware
Format: PDF
As the VLSI technologies scale down to the sub-wavelength lithographic regime, the process parameter variations lead to severe variability of chip performances. Among many process parameter variations, the gate length variation is one of the most important sources of circuit performance variation. This paper proposes a gate layout pattern regularity enhancement method to reduce the systematic variation of the gate Critical Dimensions (CD). The proposed method performs a de-compaction of a cell layout considering the on-pitch constraints and enhances the pattern regularity under given timing constraints using linear programming.

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