Timing-Constrained I/O Buffer Placement for Flip-Chip Designs

Provided by: edaa
Topic: Hardware
Format: PDF
With the increase of circuit complexity and the decrease of feature size, the dramatic demand for I/O counts becomes a significant issue in VLSI designs. Due to inappropriate assignment of bump pads or improper placement of I/O buffers, the configured delays of I/O signals may not satisfy the timing requirement inside die core. In this paper, the problem of timing-constrained I/O buffer placement in an area-IO flip-chip design is firstly formulated. Furthermore, an efficient two-phase approach is proposed to place I/O buffers onto feasible buffer locations between I/O pins and bump pads with the consideration of the timing constraints.

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