Timing-Driven Variation-Aware Partitioning and Optimization of Mixed Static-Dynamic CMOS Circuits

Provided by: Scientific Research Publishing
Topic: Hardware
Format: PDF
The advancement in CMOS technology has surpassed the progress in computer aided design tools, creating an avenue for new design optimization flows. In this paper, the authors present a design level transistor sizing based timing optimization algorithms for mixed-static-dynamic CMOS logic designs. This optimization algorithm performs timing optimization through partitioning a design into static and dynamic circuits based on timing critical paths, and are further extended through a process variation aware circuit level timing optimization algorithm for dynamic CMOS circuits.

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