Provided by: University of Calgary
Date Added: Jan 2014
In timing signoff for leading-edge SOCs, even few-picosecond timing violations will not only increase design turnaround time, but also degrade design quality (e.g., through power increase from insertion of extra buffers). Conventional flip-flop timing models have fixed values of setup/hold times and clock-to-q (c2q) delay, with some advanced \"Setup-Hold Pessimism Reduction\" (SHPR) methodologies exploiting multiple setup-hold pairs in the timing model. In this paper, the authors propose to use multiple timing models to give more flexibility at timing path boundaries, thus recovering significant \"Free\" margins and reducing the number of timing violations that require unnecessary fixes.