Timing Optimization and Noise Tolerance Dynamic CMOS Logic Design

Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
Dynamic CMOS logic circuits are used in high performance VLSI chips in order to achieve very high system performance. These circuits require less number of transistors as compare to CMOS logic circuits. But, they suffer from limitations such as noise tolerance, charge leakage and power consumption. This noise induce in circuits will affect the performance of dynamic circuits. The authors' paper base on noise of MOSFET in contrast to the conventional method which measures drain current noise of MOSFET and divides it by MOSFET trans-conductance.

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