TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems
Three-dimensional stacked wide I/O DRAMs have been proposed as a promising solution to overcome the pin-limited memory performance growth, the power vs. bandwidth dilemma and the memory wall. This new DRAM architecture and organization requires a new generation of DRAM memory controllers. In this paper, the authors present a new methodology using virtual platforms to model the backend of a 3D-DRAM memory subsystem (channel controller and wide I/O DRAM) with special SystemC TLM2.0 phase extensions.
Provided by: Association for Computing Machinery Topic: Storage Date Added: Dec 2012 Format: PDF