Toward a Scalable Test Methodology for 2D-Mesh Network-on-Chips

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Provided by: edaa
Topic: Hardware
Format: PDF
In this paper, the authors present a BIST strategy for testing the Network-on-Chip (NoC) interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the NoC are tested with BIST, running at full clock-speed, and in a functional-like mode. The BIST is carried out as a go/no-go BIST operation at start up, or on command. It is shown that the proposed methodology can be applied for different implementations of deflecting switches, and that the test time is limited to a few thousand-clock cycles with fault coverage close to 100%.
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