University of Calgary
As technology scales, wire delay due to interconnect Resistance (R) and Capacitance (C) is increasing. Thus, improvement of middle-of-line and Back-End-Of-Line (BEOL) materials and process technology (e.g., to achieve reduced barrier material thickness or dielectric permittivity) has always been a key goal in the technology roadmap. However, to date there has not been any systematic quantification of the value of BEOL technology improvements on Integrated Circuit (IC) design metrics. In this paper, the authors create a framework to study the impact of improvements in interconnect technology on IC designs.