Towards a Parameterizable Cycle-Accurate ISS in ArchC
With the increase in the design complexity of MPSoC architectures, flexible and accurate processor simulators became a necessity for exploring the vast design space solutions. In this paper, the authors present a flexible cycle-accurate ISS model based on ArchC 2.0 language. The model can have a variable pipeline depth and can be integrated easily in any SoC design based on SystemC. Its performance and capabilities are demonstrated by running MiBench embedded benchmark suite, while extracting pipeline statistics for each application.