Current processors are optimized for average case performance, often leading to a high Worst-Case Execution Time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper, the authors present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dual-issue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler.