Vienna University of Technology
As transient error rates are growing due to smaller feature sizes, designing reliable synchronous circuits becomes increasingly challenging. Asynchronous logic design constitutes a promising alternative with respect to robustness and stability. In particular, delay-insensitive asynchronous circuits provide interesting properties, like an inherent resilience to delay-faults. This paper presents a new approach for comparing the robustness of synchronous and asynchronous logic. In order to ensure comparability, the authors have developed a tool to automatically transform synchronous designs into their asynchronous counterparts while preserving structural and functional equivalence.