Towards Highly Parallel Event Processing through Reconfigurable Hardware

The authors observe that event processing is at the core of many data management applications such as real-time network analysis and algorithmic trading. Furthermore, to enable the high-frequency and low-latency requirements of these applications, they presented an efficient event processing platform over reconfigurable hardware that exploits the high degrees of hardware parallelism for achieving line-rate processing. In brief, the success of their fpga-ToPSS framework is through the use of reconfigurable hardware (i.e., FPGAs) that enables hardware acceleration using custom logic circuits and elimination of OS layer latency through on-board event processing together with hardware parallelism and novel horizontal data partitioning scheme.

Provided by: Association for Computing Machinery Topic: Hardware Date Added: Jun 2011 Format: PDF

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