Towards Scalable, Energy-Efficient, Bus-Based On-Chip Networks

Provided by: The University of Tulsa
Topic: Hardware
Format: PDF
It is expected that future on-chip networks for many-core processors will impose huge overheads in terms of energy, delay, complexity, verification effort, and area. There is a common belief that the bandwidth necessary for future applications can only be provided by employing packet switched networks with complex routers and a scalable directory-based coherence protocol. The authors posit that such a scheme might likely be overkill in a well designed system in addition to being expensive in terms of power because of a large number of power-hungry routers.

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