Trade-Offs in Designing High-Performance Digital Adder Based on Heterogeneous Architecture
To design an efficient integrated circuit in terms of area, power and speed is one of the challenging task in modern VLSI design field. In the past decade numbers of research have been carried out to optimize design based on area, speed and power utilization. In this paper, the authors discuss about performance analysis of different available adder architectures has been carried out and then, they proposed a heterogeneous architecture, which composed of four different sub adders to design an adder unit in order to demonstrate trade-offs between performance parameters i.e. area, power and speed.