TRAIN: A Virtual Transaction Layer Architecture for TLM-Based HW/SW Codesign of Synthesizable MPSoC

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Provided by: European Design and Automation Association
Topic: Hardware
Format: PDF
The authors' concept of Virtual Transaction Layer (VTL) architecture allows to directly map transaction-level communication channels onto a synthesizable multiprocessor SoC implementation. The VTL is above the physical MPSoC communication architecture, acting as a hardware abstraction layer for both HW and SW components. TLM channels are represented by virtual channels which efficiently route transactions between SW and HW entities through the on-chip communication network with respect to quality-of-service and real-time requirements. The goal is to methodically simplify MPSoC design by systematic HW/SW interface abstraction, thus enabling early SW verification, rapid prototyping and fast exploration of critical design issues.
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