Transactional Memory Architecture and Implementation for IBM System z

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Over the last years, the number of CPU cores on a chip and the number of CPU cores connected to a shared memory have grown significantly to support growing workload capacity demand. The authors present the introduction of transactional memory into the next generation IBM System z CPU. They first describe the instruction-set architecture features, including requirements for enterprise-class software RAS. They then describe the implementation in the IBM zEnterprise EC12 (zEC12) microprocessor generation, focusing on how transactional memory can be embedded into the existing cache design and multiprocessor shared-memory infrastructure.

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