Provided by: Universitat Politecnica de Catalunya
In this paper, the implementation of signal processing circuits on a novel trans-linear Field-Programmable Analog Array (FPAA) test chip is reported. The FPAA test chip is based on a 0.35micron, fully CMOS trans-linear element, which is the core block of a reconfigurable analog cell. The FPAA embeds a 5x5 cell array. As implementation examples, a four-quadrant multiplier with five decade dynamic range and a programmable fourth-order low-pass filter with up to 7MHz bandwidth have been mapped on the trans-linear FPAA. 14 cells have been used for the four-quadrant multiplier while 18 cells were needed for the fourth-order low-pass filter.