Tri-State Buffer with Common Data Bus

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Provided by: International Journal of Engineering Research and Applications (IJERA)
Topic: Hardware
Format: PDF
For the recent CMOS feature sizes power dissipation becomes an overriding concerns for VLSI circuit design. The authors propose a novel approach named tri-state buffer with common data bus which reduces the total power & delay of elastic buffer. The paper presents a design and implementation of tri-state buffer mechanism. This design offers also the advantage of third state (high impedance state) of tri-state buffer. The proposed elastic buffer design using tri-state buffer is implemented in cadence tools.
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