Association for Computing Machinery
In this paper, the authors focus on low-power clock network design for 3D ICs, where Through-Silicon Vias (TSVs) form a regular 2-dimensional array. This TSV array style is shown to be more manufacturable and practical than layouts with TSVs located at irregular spots. However, due to limited TSV resources in TSV arrays, TSV utilization in a 3D clock network significantly affects the final clock power. A straightforward extension on existing works for TSV arrays cannot guarantee power efficiency. Therefore, they develop a Decision-Tree-based Clock Synthesis (DTCS) method to generate low-power and reliable clock networks by efficiently exploring the entire solution space for the best TSV array utilization.