Two New Low-Power and High-Performance Full Adders
Two new low-power, and high-performance 1- bit full adder cells are proposed in this paper. These cells are based on low-power XOR/XNOR circuit and majority-not gate. Majority-not gate, which produces Cout (Output Carry), is implemented with an efficient method, using input capacitors and a static CMOS inverter. This kind of implementation benefits from low power consumption, a high degree of regularity and simplicity. Eight state-of-the-art 1-bit full adders and two proposed full adders are simulated with HSPICE using 0.18 um CMOS technology at several supply voltages ranging from 2.4v down to 0.8v.