Two Way Clock Scheme in Pipeline to Minimize the Clock Skew

Provided by: Global Journals
Topic: Hardware
Format: PDF
In most of the digital systems the clock skew decreases the performance of the digital systems in terms of providing good sensitivity or to maintain data synchronization. In the conventional pipeline system it is facing problems due to improper synchronization of clock pulses. This is a universal problem in all the digital systems mostly called jitter or skew. The propagation of information in the digital systems mainly controlled on the basis of clock pulses. In most of the digital systems the clock skew decreases the performance of the digital systems.

Find By Topic