Ultra Low Power 1-Bit Full Adder
In this paper, the authors propose a new 9 transistor 1-bit full adder. The proposed circuit performs efficiently in subthreshold region to employ in ultra low power applications. The main design objective for this new circuit is low power consumption and full voltage swing at a low supply voltage. The proposed cell also remarkably improves the power consumption, power delay product and has better noise immunity when compared to the existing deigns. All simulations are performed on 45nm standard models on Tanned EDA tool version 12.6.