Ultra Low Power Logic Gates

In this paper, implementation of all the basic logic gates is presented using 180nm CMOS technology with a very low voltage of 0.7V. Ideally, logic family should not dissipate power, have zero propagation delay, controlled rise and fall times with noise immunity. The property of CMOS closely approaches these characteristics. Another desirable characteristic of CMOS are its robustness with respect to voltage and size scaling. Though, with all the desirable characteristics of CMOS when it is implemented in the field of VLSI design there is always a trade-off between area, power dissipation and speed of operation.

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International Journal of Emerging Technology and Advanced Engineering (IJETAE)