Understanding the Impact of 3D Stacked Layouts on ILP

Provided by: The University of Tulsa
Topic: Hardware
Format: PDF
The vertical stacking of dies allows microprocessor circuits to be implemented across three dimensions. This allows a reduction in distances that signals must travel. Interconnects in future technologies are known to be a major bottleneck for performance and power. 3D die-stacked chips can alleviate the penalties imposed by long wires within micro-processor circuits. Many recent studies have attempted to partition each microprocessor structure across three dimensions to reduce their access times. In this paper, the authors implement each microprocessor structure on a single 2D die and leverage 3D to reduce the lengths of wires that communicate data between microprocessor structures within a single core.

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