Institute of Electrical & Electronic Engineers
The automation of custom hardware design often focuses on hardware optimizations for smaller portions of code that dominate the design execution. The same presumption can be stated for custom processor design. The data path of the processor can be well optimized for particular blocks of code that are formed during control flow extraction. However, larger source codes can have tens of blocks that result from Control Flow Graph (CFG). The authors implemented a global semi-automated flow that hierarchically forms the set of blocks which contributions are modeled into processor architecture. Resulting processor model is translated to RTL description and implemented inside FPGA logic.