Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design

Provided by: University of Florence
Topic: Storage
Format: PDF
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to characterize the interaction between Hardware Transactional Memory (HTM) design dimensions and multi-core microarchitecture configuration. In this paper, the authors investigate the use of analytical modeling techniques to build application-specific performance models for understanding the interaction between HTM and multi-core configurations across large design points and for efficiently exploring the co-design space between the two.

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